Personal computer apparatus and method for monitoring memory locations states for facilitating debugging of post and BIOS code
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 15, 1998
Grant Date -
N/A
app pub date -
Jun 27, 1994
filing date -
Jun 27, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A monitor and debugger routine operable on a personal computer for facilitating the design of power-on self-test (POST) and basic input and output system (BIOS) code. The monitor and debugger routine is invoked by POST code early in the system initialization process, before most of the system hardware devices have been initialized and before the operating system has been invoked. The monitor and debugger routine uses minimal system resources--lower memory and a serial communications controller--and is accessed via an external communications and display device connected via a serial communications link generated by the serial communications controller. As so invoked, the monitor and debugger routine can be used to facilitate the design and debugging of the remaining portions of the system initialization code, hardware interface code, suspend and resume code, video code, and other code that cannot be debugged using standard debuggers that require a functioning BIOS and an operating system to operate.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully