Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process

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United States of America Patent

PATENT NO 5851913
SERIAL NO

08655246

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Abstract

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A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

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Patent Owner(s)

Patent OwnerAddress
GLOBALFOUNDRIES INCPO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bandyopadhyay, Basab Austin, TX 56 1434
Brennan, William S Austin, TX 56 1608
Dawson, Robert Austin, TX 146 3861
Fulford, Jr H Jim Austin, TX 187 5367
Hause, Fred N Austin, TX 115 2840
Michael, Mark W Cedar Park, TX 106 2828

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