US Patent No: 5,852,726

Number of patents in Portfolio can not be more than 2000

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

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Abstract

A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA24136

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bistry, David Cupertino, CA 12 287
Dulong, Carole Saratoga, CA 73 1366
Eitan, Benny Haifa, IL 88 1223
Glew, Andrew F Madison, WA 114 2812
Kowashi, Eiichi Ryugasaki, JP 49 995
Lin, Derrick Foster City, CA 6 205
Mennemeier, Larry M Boulder Creek, CA 78 1328
Mittal, Millind South San Francisco, CA 134 2383
Peleg, Alexander D Haifa, IL 48 888
Vakkalagadda, Romamohan R Fremont, CA 4 128

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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
INTEL CORPORATION (36)
6,170,997 Method for executing instructions that operate on different data types stored in the same single logical register file 17 1997
6,192,464 Method and apparatus for decoding one or more instructions after renaming destination registers 5 1997
6,233,671 Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions 18 1998
6,230,253 Executing partial-width packed data instructions 23 1998
6,230,257 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 21 1998
6,192,467 Executing partial-width packed data instructions 23 1998
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6,263,426 Conversion from packed floating point data to packed 8-bit integer data in different architectural registers 9 1998
6,247,116 Conversion from packed floating point data to packed 16-bit integer data in different architectural registers 14 1998
6,266,686 Emptying packed data state during execution of packed data instructions 13 1999
6,792,523 Processor with instructions that operate on different data types stored in the same single logical register file 9 1999
7,216,138 Method and apparatus for floating point operations and format conversion operations 7 2001
6,751,725 Methods and apparatuses to clear state for operation of a stack 4 2001
6,425,073 Method and apparatus for staggering execution of an instruction 25 2001
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6,480,868 Conversion from packed floating point data to packed 8-bit integer data in different architectural registers 8 2001
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7,424,505 Method and apparatus for performing multiply-add operations on packed data 0 2001
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6,687,810 Method and apparatus for staggering execution of a single packed data instruction using the same circuit 2 2002
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7,395,298 Method and apparatus for performing multiply-add operations on packed data 17 2003
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7,373,490 Emptying packed data state during execution of packed data instructions 1 2004
7,149,882 Processor with instructions that operate on different data types stored in the same single logical register file 8 2004
7,509,367 Method and apparatus for performing multiply-add operations on packed data 0 2004
7,366,881 Method and apparatus for staggering execution of an instruction 0 2005
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8,396,915 Processor for performing multiply-add operations on packed data 0 2012
 
BRIDGE CROSSING, LLC (34)
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THE INVENTION SCIENCE FUND I, LLC (5)
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INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
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SUN MICROSYSTEMS, INC. (2)
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ADVANCED MICRO DEVICES, INC. (1)
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HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
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IDEA CORPORATION (1)
6,065,114 Cover instruction and asynchronous backing store switch 10 1998
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
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INFINEON TECHNOLOGIES AG (1)
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INSTITUTE FOR THE DEVELOPMENT OF EMERGING, THE (1)
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INTELLECTUAL VENTURE FUNDING LLC (1)
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KABUSHIKI KAISHA TOSHIBA (1)
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MIPS TECHNOLOGIES, INC. (1)
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SEARETE LLC (1)
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OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (1)
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