Pattern generation apparatus and method for SDRAM
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 29, 1998
Grant Date -
N/A
app pub date -
Jan 20, 1998
filing date -
Sep 6, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for the SDRAM by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two kinds of data from a pattern generator and converts the data through a predetermined logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting the column address data Y0-Y2 and the wrap address data Z0-Z2, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully