Importance

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Abstract

A data processing apparatus having a bidirectional bus circuit is provided. The data processing apparatus further includes a central logic unit and a plurality of peripheral logic units. The bidirectional bus circuit includes a plurality of bus lines for coupling the central logic unit to the peripheral logic units. Moreover, the bidirectional bus circuit includes a plurality of bidirectional data repeaters. Each of the repeaters have a plurality of data ports, wherein one of the ports is coupled to one peripheral logic unit cluster. The bidirectional data repeaters further include peripheral branch identification circuits for receiving a peripheral identification signal from the central logic unit and for generating a directioning signal responsive to the peripheral identification signal. The bidirectional data repeater further includes a directioning circuit for coupling to the data ports and to the identification means and for receiving data from one port and transmitting the data to at least another port responsive to the directioning signal.

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First Claim