Method and apparatus for determining wait states on a per cycle basis in a data processing system
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United States of America Patent
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Dec 29, 1998
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N/A
app pub date -
May 9, 1996
filing date -
May 9, 1996
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Abstract
Method and apparatus in a data processing system (10) for determining wait states on a per cycle basis. The present invention provides a wait state value (39) to a data processing system (10) indicating the number of wait states for each bus cycle. In one embodiment, a wait state pulse (81) is provided by data processing system (10), during which the wait state value (39) is provided to data processing system (10) by way of data bus (82). In response to the wait state value (39), data processing system (10) inserts a number of wait states corresponding to the wait state value (39) during the present bus cycle. In one embodiment of the present invention, a chip select signal (73) is combined with a portion of the address (83) to further partition the address range of the chip select signal (73).
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