Microarchitecture for implementing an instruction to clear the tags of a stack reference register file

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United States of America Patent

PATENT NO 5857096
SERIAL NO

08575686

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Abstract

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An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data contained in the first storage area. A first circuit is coupled to the plurality of tags which sets only the plurality of tags to an empty state responsive to receipt of a first instruction. The first instruction indicates termination of execution of instructions which operate upon the packed data stored in the first storage area. The apparatus further comprises a second circuit coupled to the plurality of tags for setting the plurality of tags to a non-empty state responsive to receipt of a second instruction (or instructions). The second instruction specifies an operation upon packed data stored in the first storage area. The second circuit further sets the plurality of tags to indicate execution of instructions which operate upon the packed data. This apparatus advantageously provides a architecture (e.g. a microarchitecture for a microprocessor) for clearing the packed data state at the end of executed blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. blocks of executed floating point instructions).

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bistry, David Cupertino, CA 12 419
Dulong, Carole Saratoga, CA 73 3130
Eitan, Benny Haifa, IL 104 3065
Kowashi, Eiichi Ryugasaki, JP 50 2158
Mennemeier, Larry Boulder Creek, CA 11 342
Mittal, Millind South San Francisco, CA 184 5720
Peleg, Alexander D Haifa, IL 51 1914

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