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Abstract

A DMA controlling device is provided. The DMA controlling device includes a DMA control register for storing an instruction, which is transmitted to the DMA controlling device by the microprocessor for the DMA transmission: a DMA count register for recording a number of DMA transmission; means for generating the address of the source memory during the DMA transmission; means for generating the address of the destination memory during the DMA transmission; a DMA data buffer for temporarily storing data of the source memory before the data of the source memory is transmitted to the destination memory; DMA arbitrating means for arbitrating a memory access priority upon the occurrence of each the DMA transmission cycle when the memory access request is received from at least one master intending to use one of the source and destination memories during the DMA transmission; and DMA engine controlling means for requesting the memory access priority from the DMA arbitrator, transmitting memory control signals to a master which has the memory access priority, and transmitting information regarding the DMA transmission frequency to a DMA count register. Therefore, the performance of a multiprocessor system requiring high speed balanced with a minimum pause time can be improved by supporting a DMA transmission cycle together with a general processor cycle.

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First Claim