Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 12, 1999
Grant Date -
N/A
app pub date -
Oct 10, 1996
filing date -
Oct 10, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of making gate array ASIC components from a master slice wafer having a first conducting layer containing logic elements, a second conducting layer containing first electrically conducting elements extending in a first direction, and a third conducting layer comprises interconnecting at least some of the logic elements to one another with a single masking process step by defining, on the third conducting layer, second conducting elements connected to the first electrically conducting elements to define connections between the logic elements.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully