Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
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United States of America Patent
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Jan 12, 1999
Grant Date -
N/A
app pub date -
Mar 12, 1997
filing date -
Mar 12, 1997
priority date (Note) -
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Abstract
An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.
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