Programmable logic array integrated circuits with enhanced cascade
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United States of America Patent
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Jan 12, 1999
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N/A
app pub date -
Jul 22, 1997
filing date -
Nov 4, 1994
priority date (Note) -
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Abstract
A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABS) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LEs are connectable to one another via cascade connectors (72) between LEs. The cascade is enhanced by providing a selector (90) that allows a cascade line from one LE to selectively be coupled to an input of an adjacent or nearby LE through a cascade logic gate (94).
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