Method and apparatus for computing minimum wirelength position (MWP) for cell in cell placement for integrated circuit chip
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United States of America Patent
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Jan 12, 1999
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app pub date -
Aug 1, 1996
filing date -
Sep 13, 1994
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Abstract
A method and apparatus for positioning a cell in a cell placement for an integrated circuit chip such that a total wirelength for interconnect nets that are connected to said cell is substantially minimum includes constructing bounding boxes around the interconnect nets with the cell excluded respectively. A median interval of the bounding boxes within which the total wirelength is substantially invariant is computed, and the cell is positioned in the median interval. Another optimization methodology, such as for minimizing interconnect congestion, is then applied to compute and position the cell in an optimum location in the median interval.
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