Efficient multiprocessing for cell placement of integrated circuits
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United States of America Patent
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Jan 12, 1999
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N/A
app pub date -
Feb 11, 1997
filing date -
Feb 11, 1997
priority date (Note) -
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Abstract
A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout of a core area of an integrated chip is disclosed. The method requires the core area to be divided into preferably a grid of rectangular regions. Then, the rectangular region is sequenced such that each region of the sequence is not adjacent to the previous or the next region of the sequence, and is sufficiently far from the previous and from the next region of the sequence such that when multiple processors are assigned to consecutive regions of the sequence to perform cell placement algorithms, area-conflicts are minimized eliminating the need to limit the distances the cells may be moved.
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