48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
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United States of America Patent
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Jan 12, 1999
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N/A
app pub date -
Jan 11, 1996
filing date -
Jan 11, 1996
priority date (Note) -
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Abstract
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.
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