Reduced instruction processor/storage controller interface
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 12, 1999
Grant Date -
N/A
app pub date -
Jan 21, 1997
filing date -
Jan 21, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully