Data-packet fifo buffer system with end-of-packet flags

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United States of America Patent

PATENT NO 5860119
SERIAL NO

08753405

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Abstract

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A packet-data FIFO buffer system comprises a FIFO buffer with a series of FIFO memory locations. Each FIFO memory location includes a data section for storing a packet data word and a flag section for storing an indication of whether or not the associated data section includes the last word of a packet. The FIFO buffer capacity is not limited to the number of maximum length packets it can hold; instead, a greater number of small packets can be stored. This increases the effectiveness of available FIFO memory and minimizes communication delays along the channels serviced by the FIFO. The FIFO design is simple and fairly self contained so that minimal external logic and control is required. In addition, an indication of the presence or absence of a complete data packet in the FIFO buffer can be easily obtained by logically adding (ORing) the contents of the flag sections.

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Patent Owner(s)

  • VLSI TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dockser, Kenneth A San Jose, CA 15 507

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