Processor with compiler-allocated, variable length intermediate storage
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United States of America Patent
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Jan 12, 1999
Grant Date -
N/A
app pub date -
Oct 2, 1995
filing date -
Oct 2, 1995
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Expired
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Abstract
A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.
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Patent Owner(s)
- INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Engebretsen, David Robert | Denmark, WI | 13 | 269 |
Gregor, Steven Lee | Endicott, NY | 23 | 244 |
Moudgill, Mayan | Ossining, NY | 77 | 1033 |
Willis, John Christopher | Rochester, MN | 13 | 712 |
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