Optimized structures for dummy fill mask design

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United States of America Patent

PATENT NO 5861342
SERIAL NO

08579605

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Abstract

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A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

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Patent Owner(s)

Patent OwnerAddress
NXP B VEINDHOVEN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gabriel, Calvin T Cupertino, CA 69 1787
Weling, Milind G San Jose, CA 17 284

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