Importance

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Abstract

A method is devised for packaging semiconductor chips based on a lead-on-chip (LOC) architecture which allows the size of the package to be substantially close to the chip size so as to reduce the packaging size to the minimum. The semiconductor chip is mounted based on a lead-on-chip architecture on a leadframe having a plurality of leads, a side rail, and at least a first connecting piece and a second connecting piece. In this method, the first step is to attach a ring to the leadframe. Then, the semiconductor chip is mounted on the leadframe and a plurality of wires are interconnected between the bonding pads on the semiconductor chip and the leads on leadframe. After that, a liquid epoxy is applied to the semiconductor chip so as to form a molding compound encapsulating the semiconductor chip. Finally, the side rail of the leadframe is removed from the leadframe. The step of encapsulation can be implemented either by epoxy dispensing or by print encapsulation system (PES). Compared to prior art methods, the foregoing method excludes the dambar cut and lead forming steps and uses small-scale encapsulating equipment. These benefits allows the IC packages to be more reliable and made with less manufacturing cost.

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First Claim