Fabrication method for chip size semiconductor package
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United States of America Patent
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Jan 26, 1999
Grant Date -
N/A
app pub date -
Sep 25, 1997
filing date -
Dec 28, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.
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