US Patent No: 5,864,657
Number of patents in Portfolio can not be more than 2000
Main memory system and checkpointing protocol for fault-tolerant computer system
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Jan 26, 1999
Issued date -
Nov 29, 1995
filing date -
08/564,021
serial no -
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Abstract
A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory subsystem. A checkpoint memory element, which may include one or more buffer memories and a shadow memory, is also appended to this main memory subsystem. During normal processing, an image of data written to primary memory is captured by the checkpoint memory element. When a new checkpoint is desired, thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault, the data previously captured is used to establish that checkpoint. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.
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First Claim
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International Classification(s)
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Cited Art
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