Multi-phase clock generator circuit
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United States of America Patent
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Feb 2, 1999
Grant Date -
N/A
app pub date -
Aug 22, 1997
filing date -
Aug 23, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A multi-phase clock generator for receiving an external clock signal through a PLL and for generating a plurality of internal clock signals differing in phase from each other. The multi-phase clock generator includes two large gates whose outputs are the two internal clock signals, and two latch circuits for controlling the logic gate outputs. The output from the PLL is fed forward to the logic gates so that the rise of one internal clock signal is separated from a prior fall of the other internal clock signal by a period related to the frequency of the PLL output.
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