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Abstract

A current mode digital-to-analog converter (DAC) consisting of a bias generator, a current mode scale-down section and a current mode scale-up section is presented which converts an n-bit digital input into an analog output. The bias generator ensures a constant reference current is caused to flow into both scale-down and scale-up sections of the DAC. The scale-down section uses the m lower-order bits of the n-bit digital input to generate a combined fractional current based on the reference current. The (n-m) higher-order bits of the n-bit digital input are used by the scale-up section to generate a multi-unit current based on the reference current. The fractional and multi-unit currents are simultaneously added together onto the output node to generate the desired analog output. By separating the total number of bits to be converted into a scale-down and a scale-up section, the total number of transistors is substantially decreased compared to other current mode DAC designs which typically use scale-up techniques only. The DAC circuit presented is fast, robust, and is capable of being implemented substantially in P type transistors reducing layout complexity.

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