Advanced modular cell placement system with fast procedure for finding a levelizing cut point

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United States of America Patent

PATENT NO 5870311
SERIAL NO

08671699

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Abstract

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A system for defining a cut point dividing a plurality of cells located on the surface of a semiconductor chip is disclosed herein. The surface has at least one region located thereon. The system comprises dividing each region into subregions, computing the capacity of each subregion, finding the maximum and minimum cell locations within each region, dividing the range spanning the maximum and minimum cell locations into a plurality of subintervals, calculating an index for each cell based on the subinterval containing the cell, accumulating cell heights for each subinterval, determining the values of cell heights for each region as the sum of cell heights for all prior regions, locating the minimum index such that the cell heights for each region are most closely proportional to the capacity of the associated subregion, and finding the cut line based on said minimum index and the maximum and minimum cell locations.

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Patent Owner(s)

Patent OwnerAddress
BELL SEMICONDUCTOR LLC401 N MICHIGAN AVE SUITE 1600 CHICAGO IL 60611

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Andreev, Alexander E Moskovskaga Oblast, RU 147 4411
Koford, James S San Jose, CA 78 4551
Scepanovic, Ranko San Jose, CA 165 5904

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