Importance

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Abstract

A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states. The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell. The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.

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First Claim