High performance, high bandwidth memory bus architecture utilizing SDRAMs
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United States of America Patent
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Feb 9, 1999
Grant Date -
N/A
app pub date -
May 21, 1997
filing date -
May 21, 1997
priority date (Note) -
Expired
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Abstract
A high performance, high bandwidth memory bus architecture and module. The module may be a card that includes standard synchronous DRAM (SDRAM) chips and reduces latency and pin count. Four bus pins separate input commands from data and establish parallel system operations. By maintaining 'packet' type transactions, independent memory operations can be enhanced from that of normal SDRAM operations. The architecture divides its buses into command and data inputs that are separate from output data.
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