Importance

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Abstract

A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional indirect guest branch instruction is stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt. The entry includes an indication of a location in memory of at least one semantic routine. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines. The semantic routine utilized to emulate a first type of unconditional indirect guest branch instruction calculates a speculative return address, temporarily stores the speculative return address in memory, and initiates fetching at a target address. The semantic routine utilized to emulate a second type of unconditional indirect guest branch instruction retrieves the speculative return address from memory, initiates fetching of guest instructions at the speculative return address, and thereafter calculates a correct return address.

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First Claim