System and method for reducing power consumption in an electronic circuit
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United States of America Patent
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-
Feb 9, 1999
Grant Date -
N/A
app pub date -
Oct 4, 1996
filing date -
Oct 4, 1996
priority date (Note) -
In Force
status (Latency Note)
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Abstract
While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0
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