Low voltage CMOS analog multiplier with extended input dynamic range
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United States of America Patent
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Feb 16, 1999
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N/A
app pub date -
Aug 12, 1997
filing date -
Aug 12, 1997
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Expired
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Abstract
A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.
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