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Abstract

A system for optimizing arbitration latency of a bus. The system places a bus grant idle state insertion logic block in parallel with a bus grant decision logic block. This allows the bus grant idle state insertion logic block to immediately deassert all bus grant output signals for one clock cycle as long as the bus is idle and a device has requested use of the bus. The bus grant idle state insertion logic block then changes the output of a multiplexer so as to select the bus grant output signal (which becomes valid during this state)and drives the output bus grant signal off chip thereby granting the bus to a device which requested use of the bus. The bus granting process takes two (2) clock cycles.

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First Claim