Second level cache having instruction cache parity error control
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United States of America Patent
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Feb 23, 1999
Grant Date -
N/A
app pub date -
Dec 30, 1996
filing date -
Dec 30, 1996
priority date (Note) -
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Abstract
Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.
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