Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states
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United States of America Patent
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Feb 23, 1999
Grant Date -
N/A
app pub date -
Jun 30, 1995
filing date -
Jun 30, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states. In a first embodiment of the present invention, the selected combination of states is specified as a combination of states corresponding to an access to a specified address within an associated memory. According to a second embodiment of the present invention, the selected combination of states is specified as a selected sequence of states of a subset of the number of state machines.
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