Low temperature integrated metallization process and apparatus

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United States of America Patent

PATENT NO 5877087
SERIAL NO

08561605

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Abstract

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The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

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Patent Owner(s)

  • APPLIED MATERIALS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fusen Cupestino, CA 68 3016
Guo, Ted Palo Alto, CA 36 1491
Mosely, Roderick Craig Pleasanton, CA 27 2121
Zhang, Hong Fremont, CA 835 11020

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