US Patent No: 5,877,087

Number of patents in Portfolio can not be more than 2000

Low temperature integrated metallization process and apparatus

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Abstract

The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
APPLIED MATERIALS, INC.SANTA CLARA, CA6777

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Fusen Saratoga, CA 67 1530
Guo, Ted Palo Alto, CA 37 581
Mosely, Roderick Craig Pleasanton, CA 28 741
Zhang, Hong Shenyang, CN 447 2046

Cited Art

Patent Info (Count) # Cites Year
 
APPLIED MATERIALS, INC. (5)
4,951,601 Multi-chamber integrated process system 683 1989
5,028,565 Process for CVD deposition of tungsten layer on semiconductor wafer 120 1989
5,043,299 Process for selective deposition of tungsten on semiconductor wafer 79 1989
5,043,300 Single anneal step process for forming titanium silicide on semiconductor wafer 91 1990
5,250,467 Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer 57 1991
 
TEXAS INSTRUMENTS INCORPORATED (3)
4,920,072 Method of forming metal interconnects 38 1988
4,920,073 Selective silicidation process using a titanium nitride protective layer 57 1989
5,010,032 Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects 87 1989
 
CORNELL RESEARCH FOUNDATION, INC. (2)
5,023,201 Selective deposition of tungsten on TiSi.sub.2 47 1990
5,439,731 Interconnect structures containing blocked segments to minimize stress migration and electromigration damage 72 1994
 
FUJITSU LIMITED (2)
4,985,750 Semiconductor device using copper metallization 106 1987
5,081,064 Method of forming electrical contact between interconnection layers located at different layer levels 35 1990
 
KABUSHIKI KAISHA TOSHIBA (2)
5,102,826 Method of manufacturing a semiconductor device having a silicide layer 24 1990
5,514,425 Method of forming a thin film 27 1995
 
MOTOROLA, INC. (2)
4,926,237 Device metallization, device and method 73 1988
4,994,410 Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process 115 1990
 
ADVANCED MICRO DEVICES, INC. (1)
4,960,732 Contact plug and interconnect employing a barrier lining and a backfilled conductor material 118 1989
 
AT&T BELL LABORATORIES (1)
5,102,827 Contact metallization of semiconductor integrated-circuit devices 23 1991
 
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM (1)
5,292,558 Process for metal deposition for microelectronic interconnections 65 1991
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5,250,465 Method of manufacturing semiconductor devices 32 1992
 
INMOS CORPORATION (1)
4,784,973 Semiconductor contact silicide/nitride process with control for silicide thickness 103 1987
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,585,673 Refractory metal capped low resistivity metal conductor lines and vias 103 1994
 
MICRON TECHNOLOGY, INC. (1)
5,147,819 Semiconductor metallization method 76 1991
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
5,480,836 Method of forming an interconnection structure 27 1994
 
NORTEL NETWORKS LIMITED (1)
5,354,712 Method for forming interconnect structures for integrated circuits 286 1992
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,091,339 Trenching techniques for forming vias and channels in multilayer electrical interconnects 102 1990
 
ZIV, ALAN R. (57.5 PERCENT) (1)
4,938,996 Via filling by selective laser chemical vapor deposition 36 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
APPLIED MATERIALS, INC. (21)
6,537,905 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 12 1996
6,169,030 Metallization process and method 24 1998
6,547,934 Reduction of metal oxide in a dual frequency etch chamber 3 1998
6,518,176 Method of selective formation of a barrier layer for a contact level via 1 1998
6,297,147 Plasma treatment for ex-situ contact fill 20 1998
6,605,531 Hole-filling technique using CVD aluminum and PVD aluminum integration 0 1998
7,053,002 Plasma preclean with argon, helium, and hydrogen gases 3 1998
6,352,620 Staged aluminum deposition process for filling vias 10 1999
6,656,831 Plasma-enhanced chemical vapor deposition of a metal nitride layer 15 2000
6,458,684 Single step process for blanket-selective CVD aluminum deposition 8 2000
6,528,180 Liner materials 2 2000
6,627,542 Continuous, non-agglomerated adhesion of a seed layer to a barrier layer 17 2000
6,794,311 Method and apparatus for treating low k dielectric layers to reduce diffusion 15 2001
6,627,050 Method and apparatus for depositing a tantalum-containing layer on a substrate 18 2001
6,660,135 Staged aluminum deposition process for filling vias 7 2001
6,743,714 Low temperature integrated metallization process and apparatus 1 2002
6,716,733 CVD-PVD deposition process 0 2002
7,112,528 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 3 2003
7,144,606 Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers 2 2004
7,550,055 Elastomer bonding of large area sputtering target 2 2005
7,867,900 Aluminum contact integration on cobalt silicide junction 0 2008
 
TEXAS INSTRUMENTS INCORPORATED (3)
6,143,645 Reduced temperature contact/via filling 14 1998
5,981,382 PVD deposition process for CVD aluminum liner processing 19 1998
6,355,558 Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films 30 1999
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
8,003,536 Electromigration resistant aluminum-based metal interconnect structure 0 2009
8,084,864 Electromigration resistant aluminum-based metal interconnect structure 0 2011
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (1)
5,994,217 Post metallization stress relief annealing heat treatment for ARC TiN over aluminum layers 37 1996
 
GLOBALFOUNDRIES INC. (1)
6,492,281 Method of fabricating conductor structures with metal comb bridging avoidance 31 2000
 
MICRON TECHNOLOGY, INC. (1)
7,101,779 Method of forming barrier layers 1 2003
 
MITSUBISHI DENKI KABUSHIKI KAISHA (1)
6,171,957 Manufacturing method of semiconductor device having high pressure reflow process 15 1998
 
QIMONDA AG (1)
6,361,880 CVD/PVD/CVD/PVD fill process 1 1999
 
RENESAS ELECTRONICS CORPORATION (1)
6,123,992 Method of forming aluminum interconnection layer 3 1998
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,699,790 Semiconductor device fabrication method for filling high aspect ratio openings in insulators with aluminum 2 2002
 
UNITED MICROELECTRONICS CORP. (1)
6,001,716 Fabricating method of a metal gate 12 1998