Circuitry for emulating asynchronous register loading functions
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United States of America Patent
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-
Mar 2, 1999
Grant Date -
N/A
app pub date -
Jun 4, 1997
filing date -
Apr 7, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.
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