HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices
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United States of America Patent
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Mar 2, 1999
Grant Date -
N/A
app pub date -
Aug 1, 1996
filing date -
Aug 3, 1995
priority date (Note) -
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Abstract
This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.
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