Method and apparatus for improving wireability in chip modules
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United States of America Patent
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Mar 9, 1999
Grant Date -
N/A
app pub date -
Nov 8, 1996
filing date -
Nov 8, 1996
priority date (Note) -
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Abstract
A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.
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