Interleaved interconnect for programmable logic array devices
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United States of America Patent
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Mar 9, 1999
Grant Date -
N/A
app pub date -
Dec 2, 1996
filing date -
Sep 18, 1996
priority date (Note) -
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Abstract
A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are provided between adjacent rows of the logic regions. Vertical interconnection conductors are provided between adjacent columns of the logic regions. The logic regions in adjacent rows can use the interconnection conductors between those rows. Similarly, the logic regions in adjacent columns can use the interconnection conductors between those columns. This sharing of horizontal and/or vertical conductors by the logic regions on both sides of those horizontal and/or vertical conductors makes more efficient use of the conductors, may simplify and/or shorten interconnection paths, and has other important advantages.
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