Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced
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United States of America Patent
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Mar 9, 1999
Issued Date -
N/A
app pub date -
Oct 29, 1997
filing date -
Jan 17, 1996
priority date (Note) -
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Abstract
An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enable signal. Since the state of the input buffer enable signal is changed in synchronization with the rise of the internal clock signal, the set up time of the external signal can be sufficiently ensured while current consumption of input buffer circuit can be reduced.
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