Behavioral language models for testing and verification of digital electronic circuits
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United States of America Patent
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Mar 16, 1999
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Jul 26, 1996
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Jul 26, 1996
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Abstract
A behavioral language-based methodology for the verification and testing of digital circuit designs. An automated or interactive simulation verification system can be used in accordance with the methodology to verify a digital circuit on inexpensive, simple digital circuit simulators, using behavioral languages, and achieve certain performance features found only on more costly, complex simulators.
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