Method for the 3D interconnection of packages of electronic components, and device obtained by this method
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United States of America Patent
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Mar 23, 1999
Grant Date -
N/A
app pub date -
Nov 10, 1993
filing date -
Mar 13, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for the interconnection of stacked packages encapsulating, for example, a semiconductor chip containing an integrated circuit, for example a memory. Packages with connection pins (21) are stacked and fixedly joined to each other by means of a coating of resin for example. The pins of the packages are cut so as to be flush with the faces (31, 32) of the stack (3). The connection (C) of the packages with one another and their connection to connection pads (35) of the stack is done on the faces of the stack. The connection pads are, if necessary, provided with connection pins (36).
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