Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells
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United States of America Patent
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Mar 23, 1999
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N/A
app pub date -
May 5, 1997
filing date -
May 5, 1997
priority date (Note) -
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Abstract
A parallel processing system composed of a regular array of programmable logic devices, each of which can be configured to perform any logical mapping from inputs to outputs. The configuration of each device is specified by a small program memory contained inside each device. Any device's program memory can be read or written by any other device connected to it within the array. This facilitates the development of extremely parallel systems whose configuration can be modified at runtime, while distributing control of the array throughout the entire array itself. The resulting system is thus completely self-reconfigurable, avoiding the bottlenecks and critical failure points found in inherently externally-configured systems.
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