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Abstract

A composable memory array for a programmable logic device includes a plurality of dedicated, serially coupled memory tiles. Each memory tile includes a plurality of dual-port memory cells, each having a first port and a second port, a plurality of first bit lines coupled to the first ports and a plurality of second data lines coupled to the second ports. The first and second bit lines extend across memory tiles. Each memory tile includes a plurality of first configuration circuits which allow the first bit lines of the memory tile to be coupled to the first bit lines of the previous memory tile. Thus, any number of consecutive memory tiles can be concatenated to form a memory array using the first set of bit lines. Non-consecutive memory tiles include a plurality of second configuration circuits which allow the second bit lines of the memory tile to be coupled to the second bit lines of a previous memory tile.

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First Claim