Introducing processing delay as a multiple of the time slot duration
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United States of America Patent
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Mar 23, 1999
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N/A
app pub date -
Feb 27, 1996
filing date -
Feb 27, 1996
priority date (Note) -
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Abstract
An apparatus for performance improvement of a burst mode digital wireless receiver has a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.
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