Memory device having circuitry for initializing and reprogramming a control operation feature
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United States of America Patent
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Mar 23, 1999
Issued Date -
N/A
app pub date -
Jan 13, 1997
filing date -
Apr 15, 1994
priority date (Note) -
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Abstract
A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.
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