FPGA having logic element carry chains capable of generating wide XOR functions
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United States of America Patent
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Mar 30, 1999
Issued Date -
N/A
app pub date -
Mar 14, 1997
filing date -
Feb 26, 1997
priority date (Note) -
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Abstract
An aspect of the invention provides an FPGA interconnect and logic block structure preferably included in an array of identical tiles. By allowing the complement of a carry multiplexer input signal to be another carry multiplexer input signal, an optional inverter can be formed and a carry chain running from one tile to the next can be used for generating wide XOR functions as well as other combinational functions and arithmetic functions.
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