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Abstract

The invention provides a pulse width modulation operation circuit for processing an m-bit pulse width modulation signal which is represented by a number n of sub pulse width modulation signals, where n is a divisor of m, characterized by comprising at least two equivalent pulse modulation operation circuits for individually processing the number n of sub pulse width modulation signals and outputting the processing results in the form of binary digital signals, and means for adding the binary digital signals from the pulse modulation operation circuits. The pulse modulation operation circuits include current pulse generating means for generating current pulses corresponding to the sub pulse width modulation signals, a current bus for transmitting the generated current pulses, and means for integrating the current pulses and converting the integrated current pulses into charges, and means for digitizing the sum of the charges to obtain digitized data. Alternatively, the pulse width modulation operation circuit comprises at least one pulse modulation operation circuit for processing the number n of sub pulse width modulation signals in a time-series manner and outputting the processing results in the form of binary digital signals.

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First Claim