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Abstract

A three-step delay adjustment method for a 'combine control signals' (CCS) block and related data delay blocks for a memory device (e.g., an asynchronous SRAM) is provided. The low complexity, easy delay tuning, balanced-delay CCS block is driven by slow slope control signals taken directly from the first stage (preferably not later than a weak inverter used in the hysteresis feedback portion) of stabilized trip point input buffers. The CCS block is able to generate global internal write pulses, appropriately timed with respect to circuits gating a data write to bitline access with an address transition detection (ATD) pulse, in order to provide stable, improved and balanced (between a plurality of control signals which can individually initiate and/or end a write in multiple distinct combinations) write parameter margins for the memory device. Additionally, intermediately generated signals in the CCS block are used for read-control, and a quarter-targeted data write bus enabling technique allows standby and transient current reduction in an improved trade-off with the chip enable access time for the memory device. Both the address set-up (T.sub.sa) and the address hold (T.sub.ha) margins are improved.

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First Claim