US Patent No: 5,890,192

Number of patents in Portfolio can not be more than 2000

Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

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Abstract

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An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
SANDISK TECHNOLOGIES INC.PLANO, TX1844

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cernea, Raul-Adrian Santa Clara, CA 162 4618
Lee, Douglas J San Jose, CA 31 1993
Mehrotra, Sanjay Milpitas, CA 92 9618
Mofidi, Mehrdad Fremont, CA 31 1587

Cited Art Landscape

Patent Info (Count) # Cites Year
 
SANDISK TECHNOLOGIES INC. (4)
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KABUSHIKI KAISHA TOSHIBA (3)
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ELPIDA MEMORY, INC. (1)
5,301,162 Semiconductor random access memory device having shared sense amplifiers serving as a cache memory 48 1993
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
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MITSUBISHI DENKI KABUSHIKI KAISHA (1)
4,931,999 Access circuit for a semiconductor memory 11 1988
 
RENESAS ELECTRONICS CORPORATION (1)
5,691,954 Semiconductor memory device in which data are read and written asynchronously with application of address signal 11 1996

Patent Citation Ranking

Forward Cite Landscape

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