US Patent No: 5,890,192

Number of patents in Portfolio can not be more than 2000

Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
SANDISK TECHNOLOGIES INC.PLANO, TX2337

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cernea, Raul-Adrian Cupertino, CA 125 5176
Lee, Douglas J San Jose, CA 34 2159
Mehrotra, Sanjay Milpitas, CA 81 10417
Mofidi, Mehrdad Fremont, CA 23 1762

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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ELPIDA MEMORY, INC. (1)
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SANDISK CORPORATION (2)
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MITSUBISHI DENKI KABUSHIKI KAISHA (1)
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KABUSHIKI KAISHA TOSHIBA (3)
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SANDISK TECHNOLOGIES INC. (4)
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MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
* 5,530,955 Page memory device capable of short cycle access of different pages by a plurality of data processors 22 1994
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

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INTEL CORPORATION (1)
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7,405,985 Flexible and area efficient column redundancy for non-volatile memories 18 2007
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7,502,259 On-chip data grouping and alignment 17 2007
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7,411,827 Boosting to control programming of non-volatile memory 10 2007
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7,834,386 Non-volatile memory with epitaxial regions for limiting cross coupling between floating gates 0 2008
7,807,533 Method for forming non-volatile memory with shield plate for limiting cross coupling between floating gates 4 2008
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8,332,577 Program control of a non-volatile memory 0 2008
* 2010/0146,186 Program Control of a non-volatile memory 4 2008
8,700,840 Nonvolatile memory with write cache having flush/eviction methods 2 2009
8,244,960 Non-volatile memory and method with write cache partition management methods 23 2009
8,094,500 Non-volatile memory and method with write cache partitioning 15 2009
8,040,744 Spare block management of non-volatile memories 79 2009
* 2010/0174,846 Nonvolatile Memory With Write Cache Having Flush/Eviction Methods 31 2009
8,621,323 Pipelined data relocation and improved chip architectures 0 2009
* 2009/0125,785 Pipelined Data Relocation and Improved Chip Architectures 18 2009
8,117,380 Management of non-volatile memory systems having large erase blocks 1 2009
7,768,841 Dynamic column block selection 1 2009
* 2009/0244,987 Dynamic Column Block Selection 5 2009
8,027,195 Folding data stored in binary format into multi-state format within non-volatile memory devices 27 2009
8,307,241 Data recovery in multi-level cell nonvolatile memory 16 2009
* 2010/0318,839 DATA RECOVERY IN MULTI-LEVEL CELL NONVOLATILE MEMORY 28 2009
* 8,832,353 Host stop-transmission handling 0 2009
* 2010/0257,308 HOST STOP-TRANSMISSION HANDLING 5 2009
7,974,124 Pointer based column selection techniques in non-volatile memories 2 2009
* 2010/0329,007 Pointer Based Column Selection Techniques in Non-Volatile Memories 19 2009
8,364,883 Scheduling of housekeeping operations in flash memory systems 0 2009
7,839,685 Soft errors handling in EEPROM devices 13 2009
* 2010/0020,616 Soft Errors Handling in EEPROM Devices 3 2009
* 8,301,826 Adaptive mode switching of flash memory address mapping based on host usage characteristics 3 2009
* 2010/0049,908 Adaptive Mode Switching of Flash Memory Address Mapping Based on Host Usage Characteristics 6 2009
8,102,705 Structure and method for shuffling data within non-volatile memory devices 27 2009
* 2010/0309,720 Structure and Method for Shuffling Data Within Non-Volatile Memory Devices 12 2009
8,468,294 Non-volatile memory with multi-gear control using on-chip folding of data 3 2009
8,144,512 Data transfer flows for on-chip folding 26 2009
* 2011/0153,913 Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data 9 2009
8,209,516 Method and system for dual mode access for storage devices 1 2010
8,914,703 Method for copying data in reprogrammable non-volatile memory 0 2010
8,473,813 Methods of cell population distribution assisted read margining 0 2011
* 2011/0099,438 Methods of Cell Population Distribution Assisted Read Margining 7 2011
8,416,624 Erase and programming techniques to reduce the widening of state distributions in non-volatile memories 2 2011
8,621,177 Non-volatile memory and method with phased program failure handling 0 2011
8,239,643 Non-volatile memory and method with control data management 0 2011
8,711,625 Bad column management with bit information in non-volatile memory systems 2 2011
8,228,729 Structure and method for shuffling data within non-volatile memory devices 0 2011
9,251,086 Apparatus, system, and method for managing a cache 0 2012
8,842,473 Techniques for accessing column selecting shift register with skipped entries in non-volatile memories 0 2012
8,687,421 Scrub techniques for use with dynamic read 1 2012
8,681,548 Column redundancy circuitry for non-volatile memory 0 2012
8,725,935 Balanced performance for on-chip folding of non-volatile memories 0 2012
8,750,045 Experience count dependent program algorithm for flash memory 0 2012
9,076,506 Variable rate parallel to serial shift register 0 2012
8,897,080 Variable rate serial to parallel shift register 0 2012
9,195,584 Dynamic block linking with individually configured plane parameters 0 2013
9,037,902 Flash memory techniques for recovering from write interrupt resulting from voltage fault 0 2013
8,745,322 Management of non-volatile memory systems having large erase blocks 0 2013
9,122,591 Pipelined data relocation and improved chip architectures 0 2013
9,230,689 Finding read disturbs on non-volatile memories 0 2014
9,224,502 Techniques for detection and treating memory hole to local interconnect marginality defects 0 2015
 
LONGITUDE FLASH MEMORY SYSTEMS S.A.R.L. (19)
6,763,424 Partial block data programming and reading operations in a non-volatile memory 264 2001
7,012,835 Flash memory data correction and scrub techniques 305 2003
* 2005/0073,884 Flash memory data correction and scrub techniques 66 2003
7,120,729 Automated wear leveling in non-volatile storage systems 109 2003
* 2004/0083,335 Automated wear leveling in non-volatile storage systems 18 2003
6,968,421 Partial block data programming and reading operations in a non-volatile memory 65 2004
7,818,490 Partial block data programming and reading operations in a non-volatile memory 5 2005
* 2006/0031,627 Partial block data programming and reading operations in a non-volatile memory 4 2005
7,173,852 Corrected data storage and handling methods 146 2005
7,224,607 Flash memory data correction and scrub techniques 44 2005
* 2006/0062,048 Flash memory data correction and scrub techniques 7 2005
7,552,272 Automated wear leveling in non-volatile storage systems 22 2006
* 2007/0083,698 Automated Wear Leveling in Non-Volatile Storage Systems 16 2006
7,518,919 Flash memory data correction and scrub techniques 21 2007
7,657,702 Partial block data programming and reading operations in a non-volatile memory 7 2009
8,004,895 Flash memory data correction and scrub techniques 2 2009
7,970,987 Partial block data programming and reading operations in a non-volatile memory 9 2010
8,050,095 Flash memory data correction and scrub techniques 5 2010
8,316,177 Partial block data programming and reading operations in a non-volatile memory 0 2011
* Cited By Examiner