Coherence apparatus for cache of multiprocessor
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United States of America Patent
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Mar 30, 1999
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N/A
app pub date -
Feb 7, 1996
filing date -
Mar 20, 1995
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Abstract
A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
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