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Abstract

A method for making stacked and borderless via structures on multilevel metal interconnections for integrated circuits was achieved. The method involves forming a planar InterLayer Dielectric (ILD) silicon oxide (SiO.sub.2) layer and a silicon nitride (Si.sub.3 N.sub.4) hard mask layer over a patterned first electrically conducting layer. A patterned first photoresist etch mask is then used to etch trenches in the hard mask film and partially into the ILD layer (SiO.sub.2). A second photoresist etch mask having openings extending over the trenches is used to etch vias (or contact holes) in the remaining ILD layer to the patterned first conducting layer using the hard mask to form borderless (self-aligned) vias. The high etch-rate ratio (selectivity) of the SiO.sub.2 to the Si.sub.3 N.sub.4 (>20:1) results in only shallow recesses in the Si.sub.3 N.sub.4 masking layer. A second conductive layer is deposited and chemically-mechanically polished back to the hard mask layer and overpolished to remove a shallow recess in the hard mask and metal therein. This results in coplanar borderless via structures in the ILD with improved design ground rules. The process can be repeated several times to complete the multilevel metal interconnections needed to wire-up the integrated circuit. The coplanar structure also results in excellent stacked via structures.

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